Switch-mode power supply circuits such as synchronous buck converters are well known. FIG. 1 shows a typical synchronous buck converter circuit in which an input d-c voltage Vin is applied to MOSFETs Q1 and Q2, which may be silicon or III-Nitride based devices. The node between Q1 and Q2 is connected to output inductor L and output capacitor C. The output voltage Vo is connected to the output load which has a voltage lower than that of Vin.
In operation, an integrated circuit IC, of well known structure, is connected to the gates of Q1 and Q2 as shown by dotted lines and turns Q1 and Q2 on and off at a controlled frequency to maintain a fixed predetermined output voltage at node Vo. More particularly, FET Q2 is turned on when Q1 is off, and is turned off when Q1 is off so that a current IL flows through inductor L. This drive circuit can be integrated with or separate from the MOSFETs Q1 and Q2.
Each FET Q1 and Q2 has a respective fixed threshold gate voltage VTH at which it turns on. Each threshold voltage will produce its own peak performance at different load conditions and different on/off conditions. The threshold voltage selected for each device is a trade-off value selected for acceptable performance over the range of load conditions. For example, at full output load the VTH of Q1 should be low to reduce the RDSON of Q1 and thus reduce turn on loss. At light load or no load however, the VTH of Q1 should be higher to reduce turn-off loss without the penalty of too high an RDSON loss. Thus, in some cases it would be desirable if Q1 were able to turn on with a lower VTH but turn off with a higher VTH for the lowest switching loss. However, the VTH of Q1 must be selected as a trade-off for these opposing conditions.
As to FET Q2, it would be desirable to have a high VTH for Cdv/dt immunity at turn off, but a low VTH drive at light load to minimize gate drive loss. Its VTH however, is selected at a trade-off value which would be acceptable over the range of load conditions.